文章目录 原始代码及log 📌 UVM-TLM1最小可运行示例：APB读-改-写流程概述 🧩 核心组件与角色定位 🧠 代码级深度解析 1. APB事务对象：`apb_rw.sv`（封装操作细节） 2. TLM发起方：`initiator.sv`（发起读改写） 3. TLM目标方：`target.sv`（响应读写请求） 4. 测试环境：`tb_env.sv`（组件连接） 🚀 执行流程与数据变化 🔑 关键概念速览 ⚠️ 潜在问题与改进建议 📝 课后思考与答案 🌟 IC验证场景扩展：集成寄存器模型 1. 寄存器类与寄存器块 2. APB→寄存器适配器 3. 环境中集成寄存器模型 4. 测试用例：前门访问寄存器 ✅ 总结 原始代码及log class apb_rw extends uvm_sequence_item; typedef enum { READ, WRITE} kind_e; rand bit[ 31 : 0 ] addr; rand logic[ 31 : 0 ] data; rand kind_e kind; `uvm_object_utils_begin ( apb_rw) `uvm_field_int ( addr, UVM_ALL_ON| UVM_NOPACK) ; `uvm_field_int ( data, UVM_ALL_ON| UVM_NOPACK) ; `uvm_field_enum ( kind_e, kind, UVM_ALL_ON| UVM_NOPACK) ; `uvm_object_utils_end functionnew ( string name= "apb_rw" ) ; super. new ( name) ; endfunction function stringconvert2string ( ) ; return $sformatf ( "kind=%s addr=%0h data=%0h" , kind, addr, data) ; endfunction endclass: apb_rwclass initiator extends uvm_component; uvm_tlm_b_initiator_socket#( apb_rw) sock; `uvm_component_utils ( initiator) functionnew ( string name= "initiator" , uvm_component parent= null) ; super. new ( name, parent) ; sock= new ( "sock" , this ) ; endfunction// // Execute a simple read-modify-write // virtual taskrun_phase ( uvm_phase phase) ; apb_rw rw; uvm_tlm_time delay= new ; phase. raise_objection ( this ) ; rw= apb_rw:: type_id:: create ( "rw" , , get_full_name ( ) ) ; rw. kind= apb_rw:: READ; rw. addr= 32' h0000_FF00; sock. b_transport ( rw, delay) ; // Ok to reuse the same RW instance rw. kind= apb_rw:: WRITE; rw. data= ~ rw. data; sock. b_transport ( rw, delay) ; phase. drop_objection ( this ) ; endtask endclassclass target extends uvm_component; local bit[ 31 : 0 ] m_data; uvm_tlm_b_target_socket #( target, apb_rw) sock; `uvm_component_utils ( target) functionnew ( string name= "target" , uvm_component parent= null) ; super. new ( name, parent) ; sock= new ( "sock" , this ) ; m_data= 32' hDEADBEEF; endfunction taskb_transport ( apb_rw rw, uvm_tlm_time delay) ; case ( rw. addr) 32' h0000_FF00: beginif ( rw. kind== apb_rw:: READ) rw. data= m_data; else m_data= rw. data; end endcase #5 ; endtask functionvoid start_of_simulation_phase ( uvm_phase phase) ; `uvm_info ( "TRGT/RPT/START" , $sformatf ( "m_data: 'h%h" , m_data) , UVM_NONE) endfunction functionvoid report_phase ( uvm_phase phase) ; `uvm_info ( "TRGT/RPT/FINAL" , $sformatf ( "m_data: 'h%h" , m_data) , UVM_NONE) endfunction endclassclass tb_env extends uvm_component; `uvm_component_utils ( tb_env) initiator master; target slave; functionnew ( string name= "tb_env" , uvm_component parent= null) ; super. new ( name, parent) ; endfunction functionvoid build_phase ( uvm_phase phase) ; master= initiator:: type_id:: create ( "master" , this ) ; slave= target:: type_id:: create ( "slave" , this ) ; endfunction functionvoid connect_phase ( uvm_phase phase) ; master. sock. connect ( slave. sock) ; endfunction endclass import uvm_pkg:: * ; `include"uvm_macros.svh" `include"apb_rw.sv" `include"initiator.sv" `include"target.sv" `include"tb_env.sv" program tb_run; initial beginstatic tb_env env= new ( "env" ) ; run_test ( ) ; end endprogram-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * *  UVM-TLM2 读-改-写最小验证环境概述0)
