ZYNQ7020FPGA常用模块驱动和引脚约束和常用模块代码-编程实验室

LED

set_property IOSTANDARD LVCMOS33 [get_ports LED1] set_property IOSTANDARD LVCMOS33 [get_ports LED2] set_property PACKAGE_PIN P20 [get_ports LED1] set_property PACKAGE_PIN P21 [get_ports LED2]

串口引脚约束

# UART RX 引脚约束 set_property PACKAGE_PIN M17 [get_ports UART_0_0_rxd] set_property IOSTANDARD LVCMOS33 [get_ports UART_0_0_rxd] # UART TX 引脚约束 set_property PACKAGE_PIN L17 [get_ports UART_0_0_txd] set_property IOSTANDARD LVCMOS33 [get_ports UART_0_0_txd]

ADC_AD9248模块驱动

module ADC_AD9248( input wire aclk, // AXI标准时钟 (原 i_adc_read_clk) //- ADC物理接口 input wire [13:0] i_adc_raw_data, // 从AD9248并行数据口输入 (非AXIS标准信号，保留原命名风格) //- 通道A AXI-Stream Master接口 output wire m_axis_cha_tvalid, // 通道A数据有效信号 (原 AXI_TVALID_CHA) input wire m_axis_cha_tready, // 通道A准备好接收信号 (原 AXI_TREADY_CHA) output wire signed [15:0] m_axis_cha_tdata, // 通道A的输出数据 (原 AXI_DATA_CHA) //- 通道B AXI-Stream Master接口 output wire m_axis_chb_tvalid, // 通道B数据有效信号 (原 AXI_TVALID_CHB) input wire m_axis_chb_tready, // 通道B准备好接收信号 (原 AXI_TREADY_CHB) output wire signed [15:0] m_axis_chb_tdata // 通道B的输出数据 (原 AXI_DATA_CHB) ); //================================================================================ // 3. ADC数据DDR采集 (ADC Data DDR Capture) - 逻辑未变 //================================================================================ reg signed [13:0] data_at_negedge; reg signed [13:0] data_at_posedge; //-- 上升沿数据锁存 // 仅更新了时钟名 always @(posedge aclk) begin data_at_posedge <= i_adc_raw_data; end //-- 下降沿数据锁存 // 仅更新了时钟名 always @(negedge aclk) begin data_at_negedge <= i_adc_raw_data; end assign m_axis_cha_tvalid = 1; assign m_axis_chb_tvalid = 1; // 转化为有符号数 assign m_axis_cha_tdata = {2'b00, data_at_posedge} - 16'd8192; assign m_axis_chb_tdata = {2'b00, data_at_negedge} - 16'd8192; endmodule

ADC_AD9248引脚约束

set_property PACKAGE_PIN M19 [get_ports clk_in1_0] set_property IOSTANDARD LVCMOS33 [get_ports clk_in1_0] #ADC_AD9248通道引脚 set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLK_CHA] set_property PACKAGE_PIN Y18 [get_ports ADC_CLK_CHA] set_property IOSTANDARD LVCMOS33 [get_ports {ADC_CLK_CHB[0]}] set_property PACKAGE_PIN T22 [get_ports {ADC_CLK_CHB[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[0]}] set_property PACKAGE_PIN V22 [get_ports {i_adc_raw_data_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[1]}] set_property PACKAGE_PIN W22 [get_ports {i_adc_raw_data_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[2]}] set_property PACKAGE_PIN Y20 [get_ports {i_adc_raw_data_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[3]}] set_property PACKAGE_PIN Y21 [get_ports {i_adc_raw_data_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[4]}] set_property PACKAGE_PIN AA22 [get_ports {i_adc_raw_data_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[5]}] set_property PACKAGE_PIN AB22 [get_ports {i_adc_raw_data_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[6]}] set_property PACKAGE_PIN AA21 [get_ports {i_adc_raw_data_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[7]}] set_property PACKAGE_PIN AB21 [get_ports {i_adc_raw_data_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[8]}] set_property PACKAGE_PIN AB20 [get_ports {i_adc_raw_data_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[9]}] set_property PACKAGE_PIN AB19 [get_ports {i_adc_raw_data_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[10]}] set_property PACKAGE_PIN Y19 [get_ports {i_adc_raw_data_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[11]}] set_property PACKAGE_PIN AA19 [get_ports {i_adc_raw_data_0[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[12]}] set_property PACKAGE_PIN AA16 [get_ports {i_adc_raw_data_0[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_raw_data_0[13]}] set_property PACKAGE_PIN AB16 [get_ports {i_adc_raw_data_0[13]}]

ADC_AD9226模块驱动

module ADC_AD9226( input wire aclk, input wire [11:0] i_adc_data_cha, input wire [11:0] i_adc_data_chb, //- 通道A AXI-Stream Master接口 output wire m_axis_cha_tvalid, // 通道A数据有效信号 (原 AXI_TVALID_CHA) input wire m_axis_cha_tready, // 通道A准备好接收信号 (原 AXI_TREADY_CHA) output wire signed [15:0] m_axis_cha_tdata, // 通道A的输出数据 (原 AXI_DATA_CHA) //- 通道B AXI-Stream Master接口 output wire m_axis_chb_tvalid, // 通道B数据有效信号 (原 AXI_TVALID_CHB) input wire m_axis_chb_tready, // 通道B准备好接收信号 (原 AXI_TREADY_CHB) output wire signed [15:0] m_axis_chb_tdata // 通道B的输出数据 (原 AXI_DATA_CHB) ); // AD9226 芯片官方数据手册中，芯片数据接口的定义确实比较奇葩，BIT1 定义为 //最高位，BIT12 定义为最低位，这和我们平时通常见到的定义方法确实不同。为了和官方数 //据手册的引脚定义保持一致，数据接口我们的定义也是如此，即 BIT1↔AD1（模块实物上 //标号 D0）、…、BIT12↔AD12（模块实物上标号 D11）。大家使用时候一定注意！ // 逆序实现开始 wire [11:0] reverse_data_cha; wire [11:0] reverse_data_chb; assign reverse_data_cha = { i_adc_data_cha[0], i_adc_data_cha[1], i_adc_data_cha[2], i_adc_data_cha[3], i_adc_data_cha[4], i_adc_data_cha[5], i_adc_data_cha[6], i_adc_data_cha[7], i_adc_data_cha[8], i_adc_data_cha[9], i_adc_data_cha[10], i_adc_data_cha[11] }; assign reverse_data_chb = { i_adc_data_chb[0], i_adc_data_chb[1], i_adc_data_chb[2], i_adc_data_chb[3], i_adc_data_chb[4], i_adc_data_chb[5], i_adc_data_chb[6], i_adc_data_chb[7], i_adc_data_chb[8], i_adc_data_chb[9], i_adc_data_chb[10], i_adc_data_chb[11] }; // 逆序实现结束 reg signed [11:0] data_cha; reg signed [11:0] data_chb; //-- 上升沿数据锁存 // 仅更新了时钟名 always @(posedge aclk) begin data_cha <= reverse_data_cha; data_chb <= reverse_data_chb; end assign m_axis_cha_tvalid = 1; assign m_axis_chb_tvalid = 1; // 转化为有符号数 assign m_axis_cha_tdata = {4'b0000, data_cha} - 16'd2048; assign m_axis_chb_tdata = {4'b0000, data_chb} - 16'd2048; endmodule

ADC_AD9226引脚约束

set_property PACKAGE_PIN M19 [get_ports clk_in1_0] set_property IOSTANDARD LVCMOS33 [get_ports clk_in1_0] #ADC_AD9226引脚 set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLK_CHB] set_property PACKAGE_PIN AA13 [get_ports ADC_CLK_CHB] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[0]}] set_property PACKAGE_PIN V14 [get_ports {i_adc_data_chb_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[1]}] set_property PACKAGE_PIN Y14 [get_ports {i_adc_data_chb_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[2]}] set_property PACKAGE_PIN AA14 [get_ports {i_adc_data_chb_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[3]}] set_property PACKAGE_PIN W16 [get_ports {i_adc_data_chb_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[4]}] set_property PACKAGE_PIN Y16 [get_ports {i_adc_data_chb_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[5]}] set_property PACKAGE_PIN AA17 [get_ports {i_adc_data_chb_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[6]}] set_property PACKAGE_PIN AB17 [get_ports {i_adc_data_chb_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[7]}] set_property PACKAGE_PIN W18 [get_ports {i_adc_data_chb_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[8]}] set_property PACKAGE_PIN W17 [get_ports {i_adc_data_chb_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[9]}] set_property PACKAGE_PIN V13 [get_ports {i_adc_data_chb_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[10]}] set_property PACKAGE_PIN W13 [get_ports {i_adc_data_chb_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_chb_0[11]}] set_property PACKAGE_PIN Y13 [get_ports {i_adc_data_chb_0[11]}] set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLK_CHA] set_property PACKAGE_PIN AA22 [get_ports ADC_CLK_CHA] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[0]}] set_property PACKAGE_PIN AB15 [get_ports {i_adc_data_cha_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[1]}] set_property PACKAGE_PIN Y18 [get_ports {i_adc_data_cha_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[2]}] set_property PACKAGE_PIN AA18 [get_ports {i_adc_data_cha_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[3]}] set_property PACKAGE_PIN AB16 [get_ports {i_adc_data_cha_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[4]}] set_property PACKAGE_PIN AA16 [get_ports {i_adc_data_cha_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[5]}] set_property PACKAGE_PIN AA19 [get_ports {i_adc_data_cha_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[6]}] set_property PACKAGE_PIN Y19 [get_ports {i_adc_data_cha_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[7]}] set_property PACKAGE_PIN AB19 [get_ports {i_adc_data_cha_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[8]}] set_property PACKAGE_PIN AB20 [get_ports {i_adc_data_cha_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[9]}] set_property PACKAGE_PIN AB21 [get_ports {i_adc_data_cha_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[10]}] set_property PACKAGE_PIN AA21 [get_ports {i_adc_data_cha_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {i_adc_data_cha_0[11]}] set_property PACKAGE_PIN AB22 [get_ports {i_adc_data_cha_0[11]}]

DAC_AD9764模块驱动

module DAC_AD9764( input dac_read_clk, input wire signed [15:0] s_axis_cha_tdata, // 通道A的输入数据 input wire signed [15:0] s_axis_chb_tdata, // 通道B的输入数据 output wire [13:0] dac_cha_data, output wire [13:0] dac_chb_data ); reg [13:0] Da; reg [13:0] Db; always @(posedge dac_read_clk) begin Da <= 14'b01111111111111 - s_axis_cha_tdata[15:2]; end always @(posedge dac_read_clk) begin Db <= 14'b01111111111111 - s_axis_chb_tdata[15:2]; end assign dac_cha_data = Da; assign dac_chb_data = Db; endmodule

DAC_AD9764引脚约束

set_property PACKAGE_PIN M19 [get_ports clk_in1_0] set_property IOSTANDARD LVCMOS33 [get_ports clk_in1_0] #DAC_AD9764通道A引脚 set_property IOSTANDARD LVCMOS33 [get_ports DAC_CLK_CHA] set_property PACKAGE_PIN D18 [get_ports DAC_CLK_CHA] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[0]}] set_property PACKAGE_PIN B22 [get_ports {dac_cha_data_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[1]}] set_property PACKAGE_PIN B16 [get_ports {dac_cha_data_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[2]}] set_property PACKAGE_PIN B17 [get_ports {dac_cha_data_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[3]}] set_property PACKAGE_PIN A16 [get_ports {dac_cha_data_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[4]}] set_property PACKAGE_PIN A17 [get_ports {dac_cha_data_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[5]}] set_property PACKAGE_PIN C20 [get_ports {dac_cha_data_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[6]}] set_property PACKAGE_PIN D20 [get_ports {dac_cha_data_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[7]}] set_property PACKAGE_PIN C15 [get_ports {dac_cha_data_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[8]}] set_property PACKAGE_PIN B15 [get_ports {dac_cha_data_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[9]}] set_property PACKAGE_PIN D16 [get_ports {dac_cha_data_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[10]}] set_property PACKAGE_PIN D17 [get_ports {dac_cha_data_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[11]}] set_property PACKAGE_PIN E15 [get_ports {dac_cha_data_0[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[12]}] set_property PACKAGE_PIN D15 [get_ports {dac_cha_data_0[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_cha_data_0[13]}] set_property PACKAGE_PIN C19 [get_ports {dac_cha_data_0[13]}] #DAC_AD9764通道B引脚 set_property IOSTANDARD LVCMOS33 [get_ports DAC_CLK_CHB] set_property PACKAGE_PIN B21 [get_ports DAC_CLK_CHB] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[0]}] set_property PACKAGE_PIN H20 [get_ports {dac_chb_data_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[1]}] set_property PACKAGE_PIN H19 [get_ports {dac_chb_data_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[2]}] set_property PACKAGE_PIN F18 [get_ports {dac_chb_data_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[3]}] set_property PACKAGE_PIN E18 [get_ports {dac_chb_data_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[4]}] set_property PACKAGE_PIN G17 [get_ports {dac_chb_data_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[5]}] set_property PACKAGE_PIN F17 [get_ports {dac_chb_data_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[6]}] set_property PACKAGE_PIN C18 [get_ports {dac_chb_data_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[7]}] set_property PACKAGE_PIN C17 [get_ports {dac_chb_data_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[8]}] set_property PACKAGE_PIN F19 [get_ports {dac_chb_data_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[9]}] set_property PACKAGE_PIN G19 [get_ports {dac_chb_data_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[10]}] set_property PACKAGE_PIN E19 [get_ports {dac_chb_data_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[11]}] set_property PACKAGE_PIN E20 [get_ports {dac_chb_data_0[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[12]}] set_property PACKAGE_PIN C22 [get_ports {dac_chb_data_0[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {dac_chb_data_0[13]}] set_property PACKAGE_PIN D22 [get_ports {dac_chb_data_0[13]}]

DAC_AD9767模块驱动

module DAC_AD9767( input wire [15:0] Data_CHA, input wire [15:0] Data_CHB, input wire clk, output wire wen_CHA, output wire wen_CHB, output reg [13:0] DAC_Data_CHA, output reg [13:0] DAC_Data_CHB ); always @(posedge clk) begin DAC_Data_CHA <= 14'b01111111111111 - Data_CHA[13:0]; end always @(posedge clk) begin DAC_Data_CHB <= 14'b01111111111111 - Data_CHB[13:0]; end assign wen_CHA = clk; assign wen_CHB = clk; endmodule

DAC_AD9767引脚约束

#DAC_AD9767通道A引脚 set_property IOSTANDARD LVCMOS33 [get_ports DAC_CLK_CHA] set_property PACKAGE_PIN A16 [get_ports DAC_CLK_CHA] set_property IOSTANDARD LVCMOS33 [get_ports wen_CHA_0] set_property PACKAGE_PIN A17 [get_ports wen_CHA_0] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[0]}] set_property PACKAGE_PIN C20 [get_ports {DAC_Data_CHA_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[1]}] set_property PACKAGE_PIN D20 [get_ports {DAC_Data_CHA_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[2]}] set_property PACKAGE_PIN C15 [get_ports {DAC_Data_CHA_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[3]}] set_property PACKAGE_PIN B15 [get_ports {DAC_Data_CHA_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[4]}] set_property PACKAGE_PIN D16 [get_ports {DAC_Data_CHA_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[5]}] set_property PACKAGE_PIN D17 [get_ports {DAC_Data_CHA_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[6]}] set_property PACKAGE_PIN E15 [get_ports {DAC_Data_CHA_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[7]}] set_property PACKAGE_PIN D15 [get_ports {DAC_Data_CHA_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[8]}] set_property PACKAGE_PIN C19 [get_ports {DAC_Data_CHA_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[9]}] set_property PACKAGE_PIN D18 [get_ports {DAC_Data_CHA_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[10]}] set_property PACKAGE_PIN F16 [get_ports {DAC_Data_CHA_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[11]}] set_property PACKAGE_PIN E16 [get_ports {DAC_Data_CHA_0[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[12]}] set_property PACKAGE_PIN G16 [get_ports {DAC_Data_CHA_0[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHA_0[13]}] set_property PACKAGE_PIN G15 [get_ports {DAC_Data_CHA_0[13]}] #DAC_AD9767通道B引脚 set_property IOSTANDARD LVCMOS33 [get_ports DAC_CLK_CHB] set_property PACKAGE_PIN B17 [get_ports DAC_CLK_CHB] set_property IOSTANDARD LVCMOS33 [get_ports wen_CHB_0] set_property PACKAGE_PIN B16 [get_ports wen_CHB_0] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[0]}] set_property PACKAGE_PIN F18 [get_ports {DAC_Data_CHB_0[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[1]}] set_property PACKAGE_PIN E18 [get_ports {DAC_Data_CHB_0[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[2]}] set_property PACKAGE_PIN G17 [get_ports {DAC_Data_CHB_0[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[3]}] set_property PACKAGE_PIN F17 [get_ports {DAC_Data_CHB_0[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[4]}] set_property PACKAGE_PIN C18 [get_ports {DAC_Data_CHB_0[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[5]}] set_property PACKAGE_PIN C17 [get_ports {DAC_Data_CHB_0[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[6]}] set_property PACKAGE_PIN F19 [get_ports {DAC_Data_CHB_0[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[7]}] set_property PACKAGE_PIN G19 [get_ports {DAC_Data_CHB_0[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[8]}] set_property PACKAGE_PIN E19 [get_ports {DAC_Data_CHB_0[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[9]}] set_property PACKAGE_PIN E20 [get_ports {DAC_Data_CHB_0[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[10]}] set_property PACKAGE_PIN C22 [get_ports {DAC_Data_CHB_0[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[11]}] set_property PACKAGE_PIN D22 [get_ports {DAC_Data_CHB_0[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[12]}] set_property PACKAGE_PIN B21 [get_ports {DAC_Data_CHB_0[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_Data_CHB_0[13]}] set_property PACKAGE_PIN B22 [get_ports {DAC_Data_CHB_0[13]}]

按键消抖

module key_debounce ( input wire clk, // 时钟信号 input wire KEY, // 原始按键信号 output reg KEY_value // 消抖后的一拍按下脉冲信号 ); // 寄存器定义 reg [1:0] debounce_mode = 2'd0; // 消抖状态机模式 reg [19:0] debounce_count = 20'd0; // 消抖计数器 reg [1:0] KEY_r = 2'b00; // KEY的两个时钟周期寄存器用于边沿检测 // 对按键进行打拍，用于边沿检测 always @(posedge clk) begin KEY_r[1] <= KEY_r[0]; KEY_r[0] <= KEY; end // 检测按键下降沿（从1变为0） wire KEY_NEGEDGE = (KEY_r[1] & ~KEY_r[0]) ? 1'b1 : 1'b0; // 按键消抖状态机逻辑 always @(posedge clk) begin case (debounce_mode) 2'd0: begin // 初始状态，等待按键按下 debounce_count <= 20'd0; debounce_mode <= 2'd1; KEY_value <= 1'b0; end 2'd1: begin // 检测到下降沿则进入消抖计数状态 if (KEY_NEGEDGE == 1'b1) begin debounce_count <= 20'd0; debounce_mode <= 2'd2; end end 2'd2: begin // 等待消抖计数时间过去 if (debounce_count >= 20'd1_000_000) begin // 达到计数后，确认按键已经按下 debounce_mode <= 2'd3; end else begin // 如果在等待过程中按键回弹（变高），则取消并重来 if (KEY == 1'b1) debounce_mode <= 2'd0; debounce_count <= debounce_count + 1'b1; end end 2'd3: begin // 消抖完成，输出有效按键信号 debounce_mode <= 2'd0; KEY_value <= 1'b1; // 只输出一拍脉冲 end default: begin debounce_mode <= 2'd0; end endcase end endmodule

sheftleft

module sheftleft#( parameter SHIFT_NUM = 4 )( input wire signed [15:0] indata, output wire signed [15:0] outdata ); assign outdata = indata <<< SHIFT_NUM; endmodule

sheftright

module sheftright#( parameter SHIFT_NUM = 4 )( input wire signed [15:0] indata, output wire signed [15:0] outdata ); assign outdata = indata >>> SHIFT_NUM; endmodule

clk_divider时钟分频模块

// clk_divider.v // 自动计算 50 % 占空比的时钟分频器 module clk_divider #( parameter CLK_IN_HZ = 50_000_000, // 输入时钟频率 (Hz) parameter CLK_OUT_HZ = 1_000_000 // 期望输出时钟频率 (Hz) )( input wire clk_in, // 输入时钟 output reg clk_out // 分频后时钟 ); localparam DIV = CLK_IN_HZ / CLK_OUT_HZ; localparam DIV_2 = CLK_IN_HZ / CLK_OUT_HZ / 2; reg [31:0] count = 0; always @(posedge clk_in) begin if(count == DIV-1) begin count <= 0; end else begin count <= count + 1; end end always @(posedge clk_in) begin if(count < DIV_2) begin clk_out <= 1; end else begin clk_out <= 0; end end endmodule